I know it’s been a running joke for years now, but jesus christ the iPhones still start at 128GB and the regular 16 is still 60Hz and USB 2.0.
I know it’s been a running joke for years now, but jesus christ the iPhones still start at 128GB and the regular 16 is still 60Hz and USB 2.0.
I really don’t understand this trend outside of profit squeezing and pushing users to cloud storage subscriptions. Right now on Amazon $120 bags you 2 TB of 6 GB/sec consumer flash storage. Don’t tell me they can’t find another 128 GB, especially with economy of scale.
The year is 2024 and storage is cheap. No excuses.
You begin your comment saying you don’t understand. And then you state the exact reasons why. You do know. You just hope your wrong. You aren’t. Google (and Apple) have become worse then Microsoft.
It’s 100% to push people to cloud services.
Tim Apple needs to make sure his services department keeps growing its subscribers. Making the shareholders happy and secure his personal bonus payments.
Packaging flash storage onto the actual
SoCSiP costs more than manufacturing the same amount of storage into an M.2 or external USB form factor, so that price can’t be directly compared. They’re making a big chunk of profit on storage upgrades, and on cloud subscriptions, but it’s not exactly cheap to give everyone 1TB of storage at that base price.That’s fascinating. My understanding was that flash storage is not physically integrated into the SoC but rather remains a separate ship that is sometimes stacked vertically.
You’re right, it’s not the same die, but the advanced packaging techniques that they keep improving (like the vertical stacking you mention) make for a much tighter set of specs for the raw flash storage silicon compared to what they might be putting in USB drives or NVMe sticks, in power consumption/temperature management, bus speeds/latency, form factor, etc.
So it’d be more accurate to describe it as a system on a package (SiP) rather than a system on a chip (SoC). Either way, that carries certain requirements that aren’t present for a standalone storage package separately soldered onto the PCB, or even storage through some kind of non-soldered swappable interface.
Thanks! It’s nice to learn something new.
Yeah, this advanced packaging stuff is pretty new, where they figured out how to make little chiplets but still put them onto the same package, connected by new tech that finally allows for high speed, low latency connections between chiplets (without causing dealbreaker temperature issues). That’s opened up a lot of progress even as improving the circuits on the silicon itself has run into engineering challenges.
So while TSMC seemingly ahead of its competition on actually printing circuits on silicon with smaller and denser features, advanced packaging tech is going a long way in allowing companies to mix and match different pieces of silicon with different strengths and functionality (for a more cost effective end solution, and making better use of the nodes that aren’t at the absolute bleeding edge).
Engineers are doing all sorts of cool stuff right now.